This invention relates generally to testing methods and apparatus and, more specifically, to complete functional testing of a relatively wide and complex data path of an absolute delay regulator located on a clock repeater chip.
An absolute delay regulator of this type is disclosed in a U.S. Pat. application Ser. No. 07/764,514 copending titled, METHOD AND APPARATUS FOR CLOCK SKEW REDUCTION THROUGH ABSOLUTE DELAY REGULATION, by Watson et al., filed herewith, which application is expressly incorporated by reference as though fully set forth herein.
A measurement circuit of the absolute delay regulator determines the intrinsic propagation delay of a clock signal processing circuit on a repeater chip by using a measurement pulse propagating through a "replica loop" and a delay line; the length of delay line traversed by the pulse in a predetermined time interval is stored in a measurement latch. The contents of the latch are decoded and transferred to a control register that controls a delay-adjusting unit; the unit also includes a tapped delay line cascaded with the processing circuitry. The delay imposed on an input clock signal by the latter delay line is adjusted by selecting one of its taps in response to the decoded contents of the latch.
The measurements made by the measurement circuit and the resulting tap selection on the tapped delay line depend on process, voltage, temperature and load (PVTL) variations to which the chip is subjected. It is difficult to simulate PVTL variations in sufficient increments to functionally test each component and connection between components of the data path for the full range of these variations. Unless all the data path circuitry can be functionally tested, the chip may fail during operation.
Therefore, it is among the objects of the invention to provide a method and apparatus for complete functional testing of a complex data path of an absolute delay regulator located on a clock repeater chip.
Another object of the present invention is to provide a method and apparatus for complete functional testing of the data path during manufacture of the chip.